![]() ![]() SotoudehHamedi-Hagh Department of Electrical Engineering Dr. ![]() ShahabArdalan Department of Electrical Engineering Dr. For more information, please contactĢ PHASE LOCKED LOOP (PLL) - BASED CLOCK AND DATA RECOVERY CIRCUIT (CDR) USING CALIBRATED DELAY FLIP FLOP (DFF) A Thesis Presented to The Faculty of the Department of Electrical Engineering San José State University In Partial Fulfillment of the Requirements for the Degree Master of Science by Sagar Waghela August 2014Ĥ The Designated Thesis Committee Approves the Thesis Titled PHASE LOCKED LOOP (PLL) - BASED CLOCK AND DATA RECOVERY CIRCUIT (CDR) USING CALIBRATED DELAY FLIP FLOP (DFF) by Sagar Waghela APPROVED FOR THE DEPARTMENT OF ELECTRICAL ENGINEERING SAN JOSÉ STATE UNIVERSITY August 2014 Dr. It has been accepted for inclusion in Master's Theses by an authorized administrator of SJSU ScholarWorks. Master's Theses This Thesis is brought to you for free and open access by the Master's Theses and Graduate Research at SJSU ScholarWorks. ![]() 1 San Jose State University SJSU ScholarWorks Master's Theses Master's Theses and Graduate Research Summer 2014 Phase Locked Loop (PLL) based Clock and Data Recovery Circuits (CDR) using Calibrated Delay Flip Flop Sagar Waghela San Jose State University Follow this and additional works at: Recommended Citation Waghela, Sagar, "Phase Locked Loop (PLL) based Clock and Data Recovery Circuits (CDR) using Calibrated Delay Flip Flop" (2014). ![]()
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